Distributing clock signals to many devices such as circuit chips with minimum skew is a difficulty in high speed digital computers. Ideally, the clock signal provides a system-wide time reference which is used to synchronize the operation of the computer logic circuitry. In practice there are a number of effects which limit the simultaneity of clock pulse arrival times at the various chips and circuits. These include, clock oscillator jitter, pulse distortion, pulse risetime degradation, pulse reflections, and asymmetries or length variations in the clock distribution wiring, connector and module parasitics.